As system speeds and integration levels have increased in FPGAs, power dissipation has become a major design concern. Meeting a power budget has become as important as closing timing for many system designs. FPGA computer-aided design tools that can not only accurately estimate the power of a design, but also automatically optimize power during design implementation have become important in meeting today's tight power budgets.
Among the important factors in estimating power dissipation/power consumption, is the behavior of each signal in a design. Two statistics used in characterizing the behavior of signals in a design are toggle rate and static probability. The toggle rate of a signal is the average number of times that the signal changes value per unit time. The units for toggle rate are transitions per second. A transition may be seen as a change in a signal from 1 to 0 or 0 to 1. The static probability of a signal is the fraction of time that the signal is logic 1 during a period of device operation that is being analyzed. Static probability ranges from 0 (ground) to 1 (logic high). Dynamic power increases linearly with the toggle rate as the capacitive load is charged more frequently for the logic and routing. The static power consumed by both routing and logic can sometimes be affected by the static probabilities of their input signals.
In the past, simulators and vectorless estimation models were used to derive the toggle rates and static probabilities of signals. Prior simulators typically had limited support for filtering non-physical glitches. Prior vectorless estimation models were typically limited in accuracy due to their correlation assumptions. To generate accurate results for power analysis and optimization, the signal activities that are used must be representative of the actual operating behavior of the design. Inaccurate signal toggle rate data is a large source of power estimation error.
Thus, what is needed is an efficient and effective method and apparatus for deriving signal activities for power analysis and optimization.